The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Apr. 07, 2009
Filed:
May. 08, 2007
Ajith Varghese, McKinney, TX (US);
Husam N. Alshareef, Plano, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Ajith Varghese, McKinney, TX (US);
Husam N. Alshareef, Plano, TX (US);
Rajesh Khamankar, Coppell, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides a complementary metal oxide semiconductor (CMOS) device, a method of manufacture therefor, and an integrated circuit including the same. The CMOS device (), in an exemplary embodiment of the present invention, includes a p-channel metal oxide semiconductor (PMOS) device () having a first gate dielectric layer () and a first gate electrode layer () located over a substrate (), wherein the first gate dielectric layer () has an amount of nitrogen located therein. In addition to the PMOS device (), the CMOS device further includes an n-channel metal oxide semiconductor (NMOS) device () having a second gate dielectric layer () and a second gate electrode layer () located over the substrate (), wherein the second gate dielectric layer () has a different amount of nitrogen located therein. Accordingly, the present invention allows for the individual tuning of the threshold voltages for the PMOS device () and the NMOS device ().