The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 31, 2009
Filed:
Jan. 17, 2006
Hsien-wei Chen, Sinying, TW;
Hsueh-chung Chen, Yonghe, TW;
Yi-lung Cheng, Danshuei Township, Taipei County, TW;
Shin-puu Jeng, Hsinchu, TW;
Hsien-Wei Chen, Sinying, TW;
Hsueh-Chung Chen, Yonghe, TW;
Yi-Lung Cheng, Danshuei Township, Taipei County, TW;
Shin-Puu Jeng, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu, TW;
Abstract
A method of generating a layout for a semiconductor device array is provided. A first layout is provided, comprising an active conductive feature, a boundary area surrounding the active conductive feature, and an open area other than the active conductive feature and the boundary area. A plurality of dummy templates of different pattern densities are provided, each of which comprises a plurality of dummy seeds. A second layout is generated by adding the dummy seeds on the open area according to at least one of the dummy templates.