The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 31, 2009

Filed:

Jun. 22, 2005
Applicants:

John Heck, Berkeley, CA (US);

Qing MA, San Jose, CA (US);

Quan Tran, Fremont, CA (US);

Tsung-kuan Allen Chou, San Jose, CA (US);

Semeon Altshuler, Rishon-le-Zion, IL;

Boaz Weinfeld, Jerusalem, IL;

Inventors:

John Heck, Berkeley, CA (US);

Qing Ma, San Jose, CA (US);

Quan Tran, Fremont, CA (US);

Tsung-Kuan Allen Chou, San Jose, CA (US);

Semeon Altshuler, Rishon-le-Zion, IL;

Boaz Weinfeld, Jerusalem, IL;

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and method of fabricating a through-wafer via. A first mask is formed over a first side of a first semiconductor die to define a first via area. A deep recess is etched through the first semiconductor die in the first via area and a blanket metal layer is formed over the first side including the deep recess. The blanket metal layer is removed from an outer surface of the first side of the first semiconductor die while retaining a portion of the blanket metal layer within the deep recess.


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