The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Mar. 24, 2009

Filed:

May. 11, 2007
Applicants:

Hideo Yamagata, Tokyo, JP;

Takeyoshi Koumoto, Tokyo, JP;

Kenji Atsuumi, Tokyo, JP;

Yoichi Negoro, Tokyo, JP;

Tatsushiro Hirata, Tokyo, JP;

Takashi Noguchi, Tokyo, JP;

Inventors:

Hideo Yamagata, Tokyo, JP;

Takeyoshi Koumoto, Tokyo, JP;

Kenji Atsuumi, Tokyo, JP;

Yoichi Negoro, Tokyo, JP;

Tatsushiro Hirata, Tokyo, JP;

Takashi Noguchi, Tokyo, JP;

Assignee:

Sony Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/322 (2006.01); H01L 21/22 (2006.01); H01L 21/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

In a vapor-phase growth method in which a silicon-germanium mixed crystal layer is deposited on a semiconductor substrate, the vapor-phase growth method comprises a first step of introducing silicon raw material gas into a reaction furnace in such a manner that a silicon raw material gas partial pressure increases in proportion to a time to thereby deposit a first semiconductor layer of a silicon layer on the semiconductor substrate under reduced pressure, a second step of introducing silicon raw material gas and germanium raw material gas into the reaction furnace in such a manner that a desired germanium concentration may be obtained to thereby deposit a second semiconductor layer of a silicon-germanium mixed crystal layer on the first semiconductor layer under reduced pressure and a third step of introducing silicon raw material gas into the reaction furnace under reduced pressure to thereby deposit a third semiconductor layer of a silicon layer on the second semiconductor layer. Thus, there can be obtained a semiconductor layer in which a misfit dislocation can be improved.


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