The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 17, 2009
Filed:
Dec. 09, 2004
Yoshihisa Matsubara, Sagamihara, JP;
Hiromichi Suzuki, Katsushika, JP;
Wahei Kitamura, Nakano, JP;
Kosho Akiyama, Nishitokyo, JP;
Seiji Kato, Chiba, JP;
Yoshihisa Matsubara, Sagamihara, JP;
Hiromichi Suzuki, Katsushika, JP;
Wahei Kitamura, Nakano, JP;
Kosho Akiyama, Nishitokyo, JP;
Seiji Kato, Chiba, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
To prevent semiconductor chips from adhering to the trays during transport, a method is employed which transports semiconductor chips in the following state. When trays provided with a plurality of accommodating portions having a recessed cross section for accommodating semiconductor chips on a main surface thereof are stacked in a plurality of stages, the semiconductor chips are accommodated in spaces defined by the accommodating portions formed over the main surface of the lower-stage tray and corresponding accommodating portions formed over the back surface of the upper-stage tray. Here, on bottom surfaces of the accommodating portions formed over the back surface of the upper-stage tray, isolated projections having a height which prevents the projections from coming into contact with the semiconductor chips are arranged in a scattered manner. In this way, it is possible to prevent the semiconductor chips from adhering to the back surface of the upper-stage tray.