Semiconductor package substrate fabrication method

Abstract

An integrated circuit substrate having embedded lands with etching and plating control features provides improved manufacture of a high-density and low cost mounting and interconnect structure for integrated circuits. The integrated circuit substrate is formed by generating channels in a dielectric material, adding conductive material to fill the channels and then planarizing the conductive material, so that conductors are formed beneath the surface of the dielectric material. Lands are formed with feature shapes that reduce a dimpling effect at etching and/or an over-deposit of material during plating, both due to increased current density at the relatively larger land areas. Feature shapes may be a grid formed with line sizes similar to those employed to form conductive interconnects, so that all features on the substrate have essentially the same line width. Alternatively, and in particular for circular pads such as solderball attach lands, sub-features may be radially disposed around a central circular area and connected with channels formed as interconnect lines that connect the sub-features to the central circular area. Connection of the lands may be made using vias or by other conductive channels forming electrical interconnect lines.