The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Mar. 03, 2009
Filed:
Nov. 14, 2006
Masayuki Ichige, Yokohama, JP;
Koji Hashimoto, Yokohama, JP;
Tatsuaki Kuji, Fukaya, JP;
Seiichi Mori, Ota-ku, JP;
Riichiro Shirota, Fujisawa, JP;
Yuji Takeuchi, Yokohama, JP;
Koji Sakui, Setagaya-ku, JP;
Masayuki Ichige, Yokohama, JP;
Koji Hashimoto, Yokohama, JP;
Tatsuaki Kuji, Fukaya, JP;
Seiichi Mori, Ota-ku, JP;
Riichiro Shirota, Fujisawa, JP;
Yuji Takeuchi, Yokohama, JP;
Koji Sakui, Setagaya-ku, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A nonvolatile semiconductor memory which is configured to include a plurality of word lines disposed in a row direction; a plurality of bit lines disposed in a column direction perpendicular to the word lines; memory cell transistors having a charge storage layer, provided in the column direction and an electronic storage condition of the memory cell transistor configured to be controlled by one of the plurality of the word lines connected to the memory cell; a plurality of first select transistors, each including a gate electrode, selecting the memory cell transistors provided in the column direction, arranged in the column direction and adjacent to the memory cell transistors at a first end of the memory cell transistors; and a first select gate line connected to each of the gate electrodes of the first select transistors.