The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 24, 2009
Filed:
Nov. 22, 2006
Applicants:
Zuoguo Wu, Santa Clara, CA (US);
Fenardi Thenus, Portland, OR (US);
Sanjay Dabral, Palo Alto, CA (US);
Inventors:
Zuoguo Wu, Santa Clara, CA (US);
Fenardi Thenus, Portland, OR (US);
Sanjay Dabral, Palo Alto, CA (US);
Assignee:
Intel Corporation, Santa Clara, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03L 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract
Frequency multiplying delay-locked loop techniques are described in which a plurality of phase shifted signals are generated utilizing a delay-locked loop circuit having a clock multiplication, the phase shifted signals having increased frequency relative to the incoming signal. The phase-shifted signals being generated by the delay-locked loop in order to position the clock to an optimal detection point of incoming data signals.