The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2009
Filed:
Sep. 12, 2006
Wan Jae Park, Fishkill, NY (US);
Jae Hak Kim, Fishkill, NY (US);
Tong Qing Chen, Singapore, SG;
Yi-hsiung Lin, Taipei, TW;
Wan Jae Park, Fishkill, NY (US);
Jae Hak Kim, Fishkill, NY (US);
Tong Qing Chen, Singapore, SG;
Yi-hsiung Lin, Taipei, TW;
Samsung Electronics Co., Ltd., , KR;
Chartered Semiconductor Manufacturing, Ltd., Singapore, SG;
International Business Machines Corporation, Armonk, NY (US);
Abstract
Methods of forming electrical interconnect structures include forming a dielectric layer on a semiconductor substrate and forming a hard mask layer on the dielectric layer. A photoresist layer is patterned on an upper surface of the hard mask layer. This patterned photoresist layer is used as an etching mask during a step to selectively etch the hard mask layer and define an opening therein. This opening exposes the first dielectric layer. The patterned photoresist layer is then stripped from the hard mask layer using an ashing process that exposes the upper surface of the hard mask layer. Following this ashing process, a portion of the first dielectric layer extending opposite the opening is selectively etched using the hard mask layer as an etching mask. During this selective etching step, polymer residues are accumulated directly on the upper surface of the hard mask layer. These polymer residues may operate to increase a degree of selectively and inhibit recession of the hard mask layer during the step of selectively etching the first dielectric layer.