The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2009

Filed:

Jan. 11, 2005
Applicants:

Jae-hoon Jang, Gyeonggi-do, KR;

Soon-moon Jung, Gyeonggi-do, KR;

Kun-ho Kwak, Gyeonggi-do, KR;

Byung-jun Hwang, Gyeonggi-do, KR;

Inventors:

Jae-Hoon Jang, Gyeonggi-do, KR;

Soon-Moon Jung, Gyeonggi-do, KR;

Kun-Ho Kwak, Gyeonggi-do, KR;

Byung-Jun Hwang, Gyeonggi-do, KR;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01);
U.S. Cl.
CPC ...
Abstract

Semiconductor integrated circuits that include thin film transistors (TFTs) and methods of fabricating such semiconductor integrated circuits are provided. The semiconductor integrated circuits may include a bulk transistor formed at a semiconductor substrate and a first interlayer insulating layer on the bulk transistor. A lower TFT may be on the first interlayer insulating layer, and a second interlayer insulating layer may be on the lower TFT. An upper TFT may be on the second interlayer insulating layer, and a third interlayer insulating layer may be on the upper TFT. A first impurity region of the bulk transistor, a first impurity region of the lower TFT, and a first impurity region of the upper TFT may be electrically connected to one another through a node plug that penetrates the first, second and third interlayer insulating layers.


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