The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2009
Filed:
Feb. 02, 2005
Gregory W. Grynkewich, Gilbert, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Kelly Kyler, Mesa, AZ (US);
Charles A. Synder, Gilbert, AZ (US);
Kenneth H. Smith, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Richard Williams, Chandler, AZ (US);
Gregory W. Grynkewich, Gilbert, AZ (US);
Brian R. Butcher, Gilbert, AZ (US);
Mark A. Durlam, Chandler, AZ (US);
Kelly Kyler, Mesa, AZ (US);
Charles A. Synder, Gilbert, AZ (US);
Kenneth H. Smith, Chandler, AZ (US);
Clarence J. Tracy, Tempe, AZ (US);
Richard Williams, Chandler, AZ (US);
EverSpin Technologies, Inc., Chandler, AZ (US);
Abstract
A method for contacting an electrically conductive layer overlying a magnetoelectronics element includes forming a memory element layer overlying a dielectric region. A first electrically conductive layer is deposited overlying the memory element layer. A first dielectric layer is deposited overlying the first electrically conductive layer and is patterned and etched to form a first masking layer. Using the first masking layer, the first electrically conductive layer is etched. A second dielectric layer is deposited overlying the first masking layer and the dielectric region. A portion of the second dielectric layer is removed to expose the first masking layer. The second dielectric layer and the first masking layer are subjected to an etching chemistry such that the first masking layer is etched at a faster rate than the second dielectric layer. The etching exposes the first electrically conductive layer.