The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
May. 23, 2007
Yasushi Koubuchi, Kokubunji, JP;
Koichi Nagasawa, Koganei, JP;
Masahiro Moniwa, Sayama, JP;
Youhei Yamada, Kodaira, JP;
Toshifumi Takeda, Tachikawa, JP;
Yasushi Koubuchi, Kokubunji, JP;
Koichi Nagasawa, Koganei, JP;
Masahiro Moniwa, Sayama, JP;
Youhei Yamada, Kodaira, JP;
Toshifumi Takeda, Tachikawa, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
Interconnections are formed over an interlayer insulating film which covers MISFETQ1 formed on the principal surface of a semiconductor substrate, while dummy interconnections are disposed in a region spaced from such interconnections. Dummy interconnections are disposed also in a scribing area. Dummy interconnections are not formed at the peripheries of a bonding pad and a marker. In addition, a gate electrode of a MISFET and a dummy gate interconnection formed of the same layer are disposed. Furthermore, dummy regions are disposed in a shallow trench element-isolation region. After such dummy members are disposed, an insulating film is planarized by the CMP method.