The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Dec. 14, 2005
Richard W. Foote, Jr., Kennedale, TX (US);
William Max Coppock, Arlington, TX (US);
Darren Lee Rust, Arlington, TX (US);
Charles A. Dark, Arlington, TX (US);
Richard W. Foote, Jr., Kennedale, TX (US);
William Max Coppock, Arlington, TX (US);
Darren Lee Rust, Arlington, TX (US);
Charles A. Dark, Arlington, TX (US);
National Semiconductor Corporation, Santa Clara, CA (US);
Abstract
A method is disclosed for controlling the formation of an interfacial oxide layer in a polysilicon emitter transistor device. The interfacial oxide layer is formed between an underlying substrate of single crystal silicon and an upper layer of polysilicon. The current gain and the emitter resistance of the transistor device are related to the thickness of the interfacial oxide layer. The oxide of the interfacial oxide layer is grown in a low pressure, low temperature pure oxygen (O) environment that greatly reduces the oxidation rate. The low oxidation rate allows the thickness of the interfacial oxide layer to be precisely controlled and sources of variation to be minimized in the manufacturing process.