The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Nov. 14, 2006
Jochen Beintner, Reutlingen, DE;
Gary B. Bronner, Stormville, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Yujun LI, Portland, OR (US);
Jochen Beintner, Reutlingen, DE;
Gary B. Bronner, Stormville, NY (US);
Ramachandra Divakaruni, Ossining, NY (US);
Yujun Li, Portland, OR (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method of fabricating a plurality of FinFETs on a semiconductor substrate in which the gate width of each individual FinFET is defined utilizing only a single etching process, instead of two or more, is provided. The inventive method results in improved gate width control and less variation of the gate width of each individual gate across the entire surface of the substrate. The inventive method achieves the above by utilizing a modified sidewall image transfer (SIT) process in which an insulating spacer that is later replaced by a gate conductor is employed and a high-density bottom up oxide fill is used to isolate the gate from the substrate.