The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2008

Filed:

May. 31, 2001
Applicants:

Toru Taniguchi, Tokyo, JP;

Isoroku Ono, Tokyo, JP;

Seiji Harada, Tokyo, JP;

Inventors:

Toru Taniguchi, Tokyo, JP;

Isoroku Ono, Tokyo, JP;

Seiji Harada, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
B24B 1/00 (2006.01); B24B 7/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

During polishing of the semiconductor wafer by using a double-sided polisher, a larger difference as compared to the prior art is created between a frictional resistance acting on a front surface of a silicon wafer from an upper surface plate side and a frictional resistance acting on a back surface of the silicon wafer from a lower surface plate side. Thereby, respective wafers can be rotated at as 0.1 - 1.0 rpm within corresponding wafer holding holes. Accordingly, the rotation of the wafer would not be suspended even if there were any defective condition induced during polishing. Further, partial variation or deviation in polishing volume particular in the outer periphery of the wafer would be hard to occur. Therefore, the polish-sagging is suppressed and thus the improved degree of flatness of the wafer could be obtained.


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