The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Mar. 30, 2006
Applicants:

Tomonori Sekiguchi, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Tatemi Ido, Tokyo, JP;

Osamu Nagashima, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Ichiro Anjo, Tokyo, JP;

Inventors:

Tomonori Sekiguchi, Tokyo, JP;

Hideki Osaka, Tokyo, JP;

Tatemi Ido, Tokyo, JP;

Osamu Nagashima, Tokyo, JP;

Mitsuaki Katagiri, Tokyo, JP;

Ichiro Anjo, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G11C 5/02 (2006.01); G11C 5/06 (2006.01); H01L 23/02 (2006.01); H01L 23/48 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor storage employs a base substrate () having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips () to () mounted on a base substrate (), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (). The interface chip () has a chip select signal generation circuit that can individually activate a plurality of memory chips () to () on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).


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