The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 09, 2008

Filed:

Mar. 25, 2003
Applicants:

Jay J. Nejedlo, Wilsonville, OR (US);

Mike Wiznerowicz, Beaverton, OR (US);

David G. Ellis, Tualatin, OR (US);

Richard J. Glass, Olympia, WA (US);

Andrew W. Martwick, Folsom, CA (US);

Theodore Z. Schoenborn, Portland, OR (US);

Inventors:

Jay J. Nejedlo, Wilsonville, OR (US);

Mike Wiznerowicz, Beaverton, OR (US);

David G. Ellis, Tualatin, OR (US);

Richard J. Glass, Olympia, WA (US);

Andrew W. Martwick, Folsom, CA (US);

Theodore Z. Schoenborn, Portland, OR (US);

Assignee:

Intel Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G01R 31/28 (2006.01); G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

According to one embodiment, a built-in self test (IBIST) architecture/methodology is disclosed. The IBIST provides for testing the functionality of an interconnect (such as a bus) between a transmitter and a receiver component. The IBIST architecture includes a pattern generator and a pattern checker. The pattern checker operates to compare a received plurality of bits (for the pattern generator) with a previously stored plurality of bits.


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