The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Nov. 30, 2006
Shui-hung Chen, Hsinchu, TW;
Jian-hsing Lee, Hsin-Chu, TW;
Yi-hsun Wu, Hsin-Chu, TW;
D. J. Perng, Hsinchu, TW;
Anthony Oates, Hsinchu, TW;
Shui-Hung Chen, Hsinchu, TW;
Jian-Hsing Lee, Hsin-Chu, TW;
Yi-Hsun Wu, Hsin-Chu, TW;
D. J. Perng, Hsinchu, TW;
Anthony Oates, Hsinchu, TW;
Taiwan Semiconductor Manufacturing Co., Hsin-Chu, TW;
Abstract
An electrostatic discharge-protected MOS structure is disclosed. An electrostatic discharge-protected MOS structure includes a semiconductor substrate of a first type, a first well of the first type formed in the semiconductor substrate, and a second well of a second type disposed adjacent to the first well. The MOS structure further includes a source region, a drain region, and an oxide layer and a polysilicon layer for forming a gate electrode of the MOS structure. In addition, the MOS structure includes a parasitic SCR comprising at least a parasitic NPN bipolar transistor and a buried layer of the second type interposed between the second well and the semiconductor substrate. The buried layer functions to lower a resistance of the semiconductor substrate during an ESD event so that ESD currents generated by the parasitic SCR are dissipated through the buried layer and the semiconductor substrate, thereby protecting the MOS structure.