The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Aug. 02, 2004
Gregory E. Howard, Dallas, TX (US);
Navin Kalidas, Houston, TX (US);
Paul J. Hundt, Garland, TX (US);
Gary P. Morrison, Garland, TX (US);
Gregory E. Howard, Dallas, TX (US);
Navin Kalidas, Houston, TX (US);
Paul J. Hundt, Garland, TX (US);
Gary P. Morrison, Garland, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
Semiconductor chip () of a ball grid array device () is mounted onto tape substrate () using attach adhesive (). The metal layer on the top surface of substrate () uses between about 30% to 90% of its area for connecting lines (), and only the remainder for members/rings () and terminals (). Routing of differential pair signals and large numbers of signals on a single layer tape package are feasible. This embodiment creates an inexpensive high performance tape ball grid array package for chip-scale devices. Terminals () serve the connection (by bonding wires or reflow bumps) to the chip contact pads. Inserted in members/rings () are the conductive pins (), which serve as anchors for the solder bodies/balls (). Pins () are substantially insensitive to the thermomechanical stresses, which occur in device () during assembly, testing and operation.