The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Sep. 02, 2005
Chien-chao Huang, Hsin-Chu, TW;
Tone-xuan Chung, Kaohsiung, TW;
Cheng-chuan Huang, Kinmen, TW;
Fu-liang Yang, Hsin-chu, TW;
Chien-Chao Huang, Hsin-Chu, TW;
Tone-Xuan Chung, Kaohsiung, TW;
Cheng-Chuan Huang, Kinmen, TW;
Fu-Liang Yang, Hsin-chu, TW;
Taiwan Semiconductor Manufacturing Co., Ltd, Hsin-Chu, TW;
Abstract
A method for forming a semiconductor device provides for forming a gate region on top of a substrate. Gate sidewall liners are formed on opposed sides of the gate region, the sidewall liners having a vertical part contacting sidewalls of the gate region and a horizontal part contacting the substrate. Recessed spacers are formed on top of the sidewall liners. The sidewall liner underneath the spacers is pulled back from the edge of the respective spacer by a predetermined distance. The recessed spacers are formed by reducing the height of the originally formed spacer. The height of the spacers is lower than a height of the gate sidewall liner and the width of the horizontal part of the sidewall liner is shorter than the width of the spacer. The reduced spacer height reduces device channel stress.