The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 02, 2008
Filed:
Apr. 25, 2006
Daniel Douriet, Round Rock, TX (US);
Anand Haridass, Austin, TX (US);
Andreas Huber, Austin, TX (US);
Colm B. O'reilly, Austin, TX (US);
Bao Gia-harvey Truong, Austin, TX (US);
Roger D. Weekly, Austin, TX (US);
Daniel Douriet, Round Rock, TX (US);
Anand Haridass, Austin, TX (US);
Andreas Huber, Austin, TX (US);
Colm B. O'Reilly, Austin, TX (US);
Bao Gia-Harvey Truong, Austin, TX (US);
Roger D. Weekly, Austin, TX (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method is provided for power delivery analysis and design for a hierarchical system. The method includes building a model corresponding to each element of the hierarchical system, compiling a repository that contains the models corresponding to each element of the hierarchical system, where the repository includes a net list, a domain list, a component list, a pin list, and a layer list. The method further includes performing optimized gridding for each element of the hierarchial system, the net list, the domain list, the component list, the pin list, and the layer list and assembling a system model from the models contained in the repository. Also, the method includes flattening the system model by converting the system model to a flattened system model that consists entirely of resistors, and running a simulation on the flattened system model.