Process for manufacturing a byte selection transistor for a matrix of non volatile memory cells and corresponding structure

Abstract

A process for manufacturing a matrix of non volatile memory cells includes forming a floating gate transistor and a cell selection transistor in a first active area, and a byte selection transistor in a second active area. A multilayer structure is deposited, comprising a gate oxide layer, a first polysilicon layer, a dielectric layer, and a second polysilicon layer. The multilayer structure is defined to form two bands, the first band defining gate regions of the byte selection transistor and the cell selection transistor, and the second band defining the gate region of the floating gate transistor. A portion of the first band extends over a portion of insulating layer adjacent to the byte selection transistor. An opening is formed in the portion of the first band, exposing the first polysilicon layer, and a conductive layer is formed in the opening, electrically coupling the first polysilicon layer with the second polysilicon layer.