The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 25, 2008

Filed:

Oct. 01, 2004
Applicants:

Sakae Koyata, Tokyo, JP;

Kazushige Takaishi, Tokyo, JP;

Tohru Taniguchi, Tokyo, JP;

Kazuo Fujimaki, Tokyo, JP;

Inventors:

Sakae Koyata, Tokyo, JP;

Kazushige Takaishi, Tokyo, JP;

Tohru Taniguchi, Tokyo, JP;

Kazuo Fujimaki, Tokyo, JP;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01); B44C 1/22 (2006.01);
U.S. Cl.
CPC ...
Abstract

Provided is a method for producing a silicon wafer whose surfaces exhibit precise flatness and minute surface roughness, and which allows one to visually discriminate between the front and rear surfaces, the method comprising a slicing step of slicing a single-crystal ingot into thin disc-like wafers, a chamfering step of chamfering the wafer, a lapping step for flattening the chamfered wafer, a mild lapping step for abrading away part of processing distortions on the rear surface of the wafer left after chamfering and lapping, a rear-surface mild polishing step for abrading away part of roughness on the rear surface of the wafer, an etching step for alkali-etching the remains of processing distortions on the front and rear surfaces of the wafer, a front-surface mirror-polishing step for mirror-polishing the front surface of the etched wafer, and a cleaning step for cleaning the mirror-polished wafer.


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