The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 25, 2008
Filed:
Apr. 13, 2006
Habib Hichri, Wappingers Falls, NY (US);
Xiao H. Liu, Croton On Hudson, NY (US);
Vincent J. Mcgahay, Poughkeepsie, NY (US);
Conal E. Murray, Yorktown Heights, NY (US);
Jawahar P. Nayak, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
Habib Hichri, Wappingers Falls, NY (US);
Xiao H. Liu, Croton On Hudson, NY (US);
Vincent J. McGahay, Poughkeepsie, NY (US);
Conal E. Murray, Yorktown Heights, NY (US);
Jawahar P. Nayak, Wappingers Falls, NY (US);
Thomas M. Shaw, Peekskill, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-tip during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.