The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Nov. 11, 2008

Filed:

Jun. 22, 2007
Applicants:

Juan A. Rosal, Plano, TX (US);

Michael Allen Ball, Richardson, TX (US);

Jayesh C. Raval, Richardson, TX (US);

Anand T. Krishnan, Farmers Branch, TX (US);

Inventors:

Juan A. Rosal, Plano, TX (US);

Michael Allen Ball, Richardson, TX (US);

Jayesh C. Raval, Richardson, TX (US);

Anand T. Krishnan, Farmers Branch, TX (US);

Assignee:
Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11C 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method of manufacturing a semiconductor device includes providing an electrical connection to a well of a MOS transistor of a static random access memory (SRAM) cell. A predetermined voltage is applied to the well using the connection to cause a threshold voltage (V) of said transistor to change. The change is employed to identify a reliability characteristic of the semiconductor device. An SRAM parameter is altered to modify the reliability characteristic.


Find Patent Forward Citations

Rosal, Juan. (2008). Method to identify or screen vmin drift on memory cells during burn-in or operation (U.S. Patent No. 7450452). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7450452

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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