The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 11, 2008
Filed:
Mar. 31, 2003
Fay Hua, Fremont, CA (US);
Gregory M. Chrysler, Chandler, AZ (US);
James G. Maveety, San Jose, CA (US);
Kramadhati V. Ravi, Atherton, CA (US);
Fay Hua, Fremont, CA (US);
Gregory M. Chrysler, Chandler, AZ (US);
James G. Maveety, San Jose, CA (US);
Kramadhati V. Ravi, Atherton, CA (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A method and apparatus to minimize thermal impedance using copper on the die or chip backside. Some embodiments use deposited copper having a thickness chosen to complement a given chip thickness, in order to reduce or minimize wafer warpage. In some embodiments, the wafer, having a plurality of chips (e.g., silicon), is thinned (e.g., by chemical-mechanical polishing) before deposition of the copper layer, to reduce the thermal resistance of the chip. Some embodiments further deposit copper in a pattern of bumps, raised areas, or pads, e.g., in a checkerboard pattern, to thicken and add copper while reducing or minimizing wafer warpage and chip stress.