The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Aug. 04, 2005
Applicants:
Takashi Whitney Orimoto, Mountain View, CA (US);
Joong Jeon, Cupertino, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Simon S. Chan, Saratoga, CA (US);
Harpreet K. Sachar, Milpitas, CA (US);
Inventors:
Takashi Whitney Orimoto, Mountain View, CA (US);
Joong Jeon, Cupertino, CA (US);
Hidehiko Shiraiwa, San Jose, CA (US);
Simon S. Chan, Saratoga, CA (US);
Harpreet K. Sachar, Milpitas, CA (US);
Assignees:
Spansion, LLC, Sunnyvale, CA (US);
Advnaced Micro Devices, Inc., Sunnyvale, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/788 (2006.01);
U.S. Cl.
CPC ...
Abstract
A semiconductor memory device may include an intergate dielectric layer of a high-K dielectric material interposed between a floating gate and a control gate. With this intergate high-K dielectric in place, the memory device may be erased using Fowler-Nordheim tunneling.