The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Nov. 17, 2006
James W. Adkisson, Jericho, VT (US);
Marc W. Cantell, Sheldon, VT (US);
James R. Elliott, Huntington, VT (US);
James V. Hart, Iii, Barre, VT (US);
Dale W. Martin, Hyde Park, VT (US);
James W. Adkisson, Jericho, VT (US);
Marc W. Cantell, Sheldon, VT (US);
James R. Elliott, Huntington, VT (US);
James V. Hart, III, Barre, VT (US);
Dale W. Martin, Hyde Park, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A semiconductor structure includes a multi-layer spacer located adjacent and adjoining a sidewall of a topographic feature within the semiconductor structure. The multi-layer spacer includes a first spacer sub-layer comprising a deposited silicon oxide material laminated to a second spacer sub-layer comprising a material that is other than the deposited silicon oxide material. The first spacer sub-layer is recessed with respect to the second spacer sub-layer by a recess distance of no greater than a thickness of the first spacer sub-layer (and preferably from about 50 to about 150 angstroms). Such a recess distance is realized through use of a chemical oxide removal (COR) etchant that is self limiting for the deposited silicon oxide material with respect to a thermally grown silicon oxide material. Dimensional integrity and delamination avoidance is thus assured for the multi-layer spacer layer.