The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Nov. 04, 2008
Filed:
Sep. 22, 2004
Glenn G. Daves, Fishkill, NY (US);
David L. Edwards, Poughkeepsie, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Frank L. Pompeo, Redding, CT (US);
Glenn G. Daves, Fishkill, NY (US);
David L. Edwards, Poughkeepsie, NY (US);
Mukta G. Farooq, Hopewell Junction, NY (US);
Frank L. Pompeo, Redding, CT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for assembling, and the resultant electronic module, includes attaching a chip to a substrate using a first solder interconnection array, and attaching a board to the substrate using a second solder interconnection array, which may be a single-melt or a dual-melt solder array. The second solder interconnection array resides entirely within a space defined between the board and substrate. A creep resistant structure is provided within this space for maintaining the defined space and optimizing integrity of the second solder interconnection array. The creep resistant structure may include an underfill material, balls, brackets, frames, collars or combinations thereof. Wherein the creep resistant structure is an underfill material, it is crucial that the substrate be attached to the board before either entirely encapsulating the second interconnection array with underfill material, or partially encapsulating the second solder interconnection array at discrete locations with underfill material.