The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Oct. 21, 2008

Filed:

May. 06, 2004
Applicants:

Rajeev Joshi, Cupertino, CA (US);

Jonathan A. Noquil, Surigao del Sur, PH;

Consuelo N. Tangpuz, Lapulapu, PH;

Inventors:

Rajeev Joshi, Cupertino, CA (US);

Jonathan A. Noquil, Surigao del Sur, PH;

Consuelo N. Tangpuz, Lapulapu, PH;

Assignee:

Fairchild Semicondcutor Corporation, South Portland, ME (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/44 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a leadframe structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead. The die attach surface and the lead surface can be in different planes.


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