The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 21, 2008
Filed:
Sep. 13, 2006
Douglas D. Coolbaugh, Highland, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Ebenezer Eshun, Newburgh, NY (US);
Vincent J. Mcgahay, Poughkeepsie, NY (US);
Anthony K. Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
Douglas D. Coolbaugh, Highland, NY (US);
Timothy J. Dalton, Ridgefield, CT (US);
Ebenezer Eshun, Newburgh, NY (US);
Vincent J. McGahay, Poughkeepsie, NY (US);
Anthony K. Stamper, Williston, VT (US);
Kunal Vaed, Poughkeepsie, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for integrating the formation of metal-insulator-metal (MIM) capacitors within dual damascene processing includes forming a lower interlevel dielectric (ILD) layer having a lower capacitor electrode and one or more lower metal lines therein, the ILD layer having a first dielectric capping layer formed thereon. An upper ILD layer is formed over the lower ILD layer, and a via and upper line structure are defined within the upper ILD layer. The via and upper line structure are filled with a planarizing layer, followed by forming and patterning a resist layer over the planarizing layer. An upper capacitor electrode structure is defined in the upper ILD layer corresponding to a removed portion of the resist. The via, upper line structure and upper capacitor electrode structure are filled with conductive material, wherein a MIM capacitor is defined by the lower capacitor electrode, first dielectric capping layer and upper capacitor electrode structure.