The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Sep. 27, 2006
Daria R. Dooling, Huntington, VT (US);
Kenneth T. Settlemyer, Jr., Poughquag, NY (US);
Jacek G. Smolinski, Jericho, VT (US);
Stephen D. Thomas, Essex Junction, VT (US);
Ralph J. Williams, Essex Junction, VT (US);
Daria R. Dooling, Huntington, VT (US);
Kenneth T. Settlemyer, Jr., Poughquag, NY (US);
Jacek G. Smolinski, Jericho, VT (US);
Stephen D. Thomas, Essex Junction, VT (US);
Ralph J. Williams, Essex Junction, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A method for implementing an ORC process to facilitate physical verification of an integrated circuit (IC) graphical design. The method includes partitioning the IC graphical design data into files by a host machine such that the files correspond to regions of interest or partitions with defined margins, dispersing the partitioned data files to available cpus within the network, processing of each job by the cpu receiving the file, wherein artifacts arising from bisection of partitioning margins during the partitioning, including cut-induced false errors, are detected and removed, and the shape-altering effects of such artifact errors are minimized and transmitting the results of processing at each cpu to the host machine for aggregate processing.