The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Sep. 24, 2007
Leonard O. Farnsworth, Iii, Lincoln, VT (US);
Michael Z. Felske, Milton, VT (US);
Pamela S. Gillia, Jericho, VT (US);
Benjamin P. Lynch, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Thomas St. Pierre, Forstinning, DE;
Tad J. Wilder, South Hero, VT (US);
Carl F. Barnhart, Ojai, CA (US);
Leonard O. Farnsworth, III, Lincoln, VT (US);
Michael Z. Felske, Milton, VT (US);
Pamela S. Gillia, Jericho, VT (US);
Benjamin P. Lynch, Colchester, VT (US);
Michael R. Ouellette, Westford, VT (US);
Thomas St. Pierre, Forstinning, DE;
Tad J. Wilder, South Hero, VT (US);
Carl F. Barnhart, Ojai, CA (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
An integrated circuit and method of testing and repairing the integrated circuit. The integrated circuit includes: a multiplicity of macro-circuits having the same function; a fuse bank, the state of the fuses storing test data indicating at least which macro-circuits failed a test; and means for preventing utilization of failing macro-circuits during operation of the integrated circuit and a method generating a partial good integrated circuit, the method including: providing an integrated circuit have a multiplicity of macro-circuits arranged in one or more groups, each macro-circuit having the same function and a fuse bank containing fuses; testing each macro-circuit prior to a fuse programming operation; programming the fuses in the fuse bank in order to store data indicating at least which macro-circuits failed the testing step; and preventing utilization of each failing macro-circuit during operation of the integrated based on the data stored in the fuse bank.