The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Oct. 07, 2008
Filed:
Sep. 13, 2006
Arunangshu Kundu, San Jose, CA (US);
Venkatesh Narayanan, San Jose, CA (US);
John Mccollum, Saratoga, CA (US);
William C. Plants, Sunnyvale, CA (US);
Arunangshu Kundu, San Jose, CA (US);
Venkatesh Narayanan, San Jose, CA (US);
John McCollum, Saratoga, CA (US);
William C. Plants, Sunnyvale, CA (US);
Actel Corporation, Mountain View, CA (US);
Abstract
A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.