The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Sep. 19, 2006
Gust Perlegos, Fremont, CA (US);
Alan L. Renninger, Kapolei, HI (US);
James Yount, Manitou Springs, CO (US);
Maria Ryan, Tynemouth, GB;
Gust Perlegos, Fremont, CA (US);
Alan L. Renninger, Kapolei, HI (US);
James Yount, Manitou Springs, CO (US);
Maria Ryan, Tynemouth, GB;
Atmel Corporation, San Jose, CA (US);
Abstract
A PMOS non-volatile memory array using SONOS transistors having program and erase threshold voltages for representing digital logic states of zero and one and selected to optimize read disturb characteristics. The threshold voltages are linearly convergent and separated by at least 0.5 volts for a charge retention time of at least 10 years, with the threshold voltages defining a window wherein a read voltage for selected memory transistors can be held flat and not intersect the threshold voltages. The lower threshold is selected to be at a zero charge state for one of the two logic levels of the memory.