The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Mar. 31, 2004
Stephen H. Tang, Pleasanton, CA (US);
Muhammad M. Khellah, Lake Oswego, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Yibin YE, Portland, OR (US);
Vivek K. DE, Beaverton, OR (US);
James W. Tschanz, Portland, OR (US);
Stephen H. Tang, Pleasanton, CA (US);
Muhammad M. Khellah, Lake Oswego, OR (US);
Dinesh Somasekhar, Portland, OR (US);
Yibin Ye, Portland, OR (US);
Vivek K. De, Beaverton, OR (US);
James W. Tschanz, Portland, OR (US);
Intel Corporation, Santa Clara, CA (US);
Abstract
A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.