The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Apr. 28, 2005
Applicants:
Antonio L. P. Rotondaro, Dallas, TX (US);
Luigi Colombo, Dallas, TX (US);
Malcolm J. Bevan, Dallas, TX (US);
Inventors:
Antonio L. P. Rotondaro, Dallas, TX (US);
Luigi Colombo, Dallas, TX (US);
Malcolm J. Bevan, Dallas, TX (US);
Assignee:
Texas Instruments Incorporated, Dallas, TX (US);
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/76 (2006.01); H01L 29/94 (2006.01); H01L 31/062 (2006.01); H01L 31/113 (2006.01); H01L 31/119 (2006.01); H01L 29/792 (2006.01);
U.S. Cl.
CPC ...
Abstract
CMOS gate dielectric made of high-k metal silicates by passivating a silicon surface with nitrogen compounds prior to high-k dielectric deposition. Optionally, a silicon dioxide monolayer may be preserved at the interface.
Rotondaro, Antonio L. P.. (2008). Integrated circuits with composite gate dielectric (U.S. Patent No. 7423326). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7423326
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile