The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 09, 2008
Filed:
Jul. 29, 2004
Jiong-ping LU, Richardson, TX (US);
Clint Montgomery, Coppell, TX (US);
Lindsey Hall, Plano, TX (US);
Donald Miles, Plano, TX (US);
Duofeng Yue, Plano, TX (US);
Thomas D. Bonifiield, Dallas, TX (US);
Jiong-Ping Lu, Richardson, TX (US);
Clint Montgomery, Coppell, TX (US);
Lindsey Hall, Plano, TX (US);
Donald Miles, Plano, TX (US);
Duofeng Yue, Plano, TX (US);
Thomas D. Bonifiield, Dallas, TX (US);
Texas Instruments Incorporated, Dallas, TX (US);
Abstract
The present invention provides a method for manufacturing a semiconductor device, and a method for manufacturing an integrated circuit including the semiconductor devices. The method for manufacturing a semiconductor device () , among other steps, includes forming a gate structure () over a substrate () and forming source/drain regions () in the substrate () proximate the gate structure (). The method further includes subjecting the gate structure () and substrate () to a dry etch process and placing fluorine in the source/drain regions to form fluorinated source/drains () subsequent to subjecting the gate structure () and substrate () to the dry etch process. Thereafter, the method includes forming metal silicide regions () in the gate structure () and the fluorinated source/drains ().