The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
Jul. 25, 2006
Chuichi Miyazaki, Akishima, JP;
Yukiharu Akiyama, Kodaira, JP;
Masnori Shibamoto, Saitama, JP;
Tomoaki Kudaishi, Komoro, JP;
Ichiro Anjoh, Koganei, JP;
Kunihiko Nishi, Kokubunji, JP;
Asao Nishimura, Koganei, JP;
Hideki Tanaka, Sagamihara, JP;
Ryosuke Kimoto, Hamura, JP;
Kunihiro Tsubosaki, Hino, JP;
Akio Hasebe, Hitachi, JP;
Chuichi Miyazaki, Akishima, JP;
Yukiharu Akiyama, Kodaira, JP;
Masnori Shibamoto, Saitama, JP;
Tomoaki Kudaishi, Komoro, JP;
Ichiro Anjoh, Koganei, JP;
Kunihiko Nishi, Kokubunji, JP;
Asao Nishimura, Koganei, JP;
Hideki Tanaka, Sagamihara, JP;
Ryosuke Kimoto, Hamura, JP;
Kunihiro Tsubosaki, Hino, JP;
Akio Hasebe, Hitachi, JP;
Renesas Technology Corp., Tokyo, JP;
Abstract
A semiconductor device includes a semiconductor chip formed with connection terminals, an elastic structure interposed between a main surface of the chip and a wiring substrate formed with wirings connected at first ends thereof to the connection terminals, and bump electrodes connected to the other ends of the wirings. The connection terminals may be at a center part or in peripheral part(s) of the chip main surface and both the elastic structure and wiring substrate are not provided at locations of connection terminals. A resin body seals at least the connection terminals and the exposed first ends of wirings (leads). In a scheme in which the connection terminals are located in a peripheral part of the chip main surface, the wiring substrate protrudes beyond the chip boundary where the connection terminals are arranged, and the resin body shape is restricted by the protruding part of the wiring substrate.