The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Sep. 02, 2008
Filed:
Aug. 25, 2005
Shu-chuan Lee, Hsin-Chu, CN;
Ming-hsiang Song, Hsin-Chu, CN;
Shao-chang Huang, Hsinchu, CN;
Yi-hsun Wu, Hsin-Chu, CN;
Kuo-feng Yu, Hsinchu, CN;
Jian-hsing Lee, Hsin-Chu, CN;
Tong-chern Ong, Chung-Ho, CN;
Shu-Chuan Lee, Hsin-Chu, CN;
Ming-Hsiang Song, Hsin-Chu, CN;
Shao-Chang Huang, Hsinchu, CN;
Yi-Hsun Wu, Hsin-Chu, CN;
Kuo-Feng Yu, Hsinchu, CN;
Jian-Hsing Lee, Hsin-Chu, CN;
Tong-Chern Ong, Chung-Ho, CN;
Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu, TW;
Abstract
Provided are an electrostatic discharge (ESD) protection device and a method for making such a device. In one example, the ESD protection device includes a Zener diode region formed in a substrate and an N-type metal oxide semiconductor (NMOS) device formed adjacent to the Zener diode region. The Zener diode region has two doped regions, a gate with a grounded potential positioned between the two doped regions, and two light doped drain (LDD) features formed in the substrate. One of the LDD features is positioned between each of the two doped regions and the gate. The NMOS device includes a source and a drain formed in the substrate and a second gate positioned between the source and the drain.