The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2008

Filed:

Nov. 08, 2005
Applicants:

Vance H. Adams, Austin, TX (US);

Paul A. Grudowski, Austin, TX (US);

Venkat R. Kolagunta, Austin, TX (US);

Brian A. Winstead, Austin, TX (US);

Inventors:

Vance H. Adams, Austin, TX (US);

Paul A. Grudowski, Austin, TX (US);

Venkat R. Kolagunta, Austin, TX (US);

Brian A. Winstead, Austin, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 29/06 (2006.01); H01L 21/31 (2006.01);
U.S. Cl.
CPC ...
Abstract

An electronic device can include a transistor structure of a first conductivity type, a field isolation region, and a layer of a first stress type overlying the field isolation region. For example, the transistor structure may be a p-channel transistor structure and the first stress type may be tensile, or the transistor structure may be an n-channel transistor structure and the first stress type may be compressive. The transistor structure can include a channel region that lies within an active region. An edge of the active region includes the interface between the channel region and the field isolation region. From a top view, the layer can include an edge the lies near the edge of the active region. The positional relationship between the edges can affect carrier mobility within the channel region of the transistor structure.


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