The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Sep. 02, 2008

Filed:

Jan. 12, 2006
Applicants:

Tatsuya Fujishima, Gunma, JP;

Mikio Fukuda, Gunma, JP;

Yuji Tsukada, Gunma, JP;

Keiji Ogata, Gunma, JP;

Izuo Iida, Tochigi, JP;

Inventors:

Tatsuya Fujishima, Gunma, JP;

Mikio Fukuda, Gunma, JP;

Yuji Tsukada, Gunma, JP;

Keiji Ogata, Gunma, JP;

Izuo Iida, Tochigi, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01);
U.S. Cl.
CPC ...
Abstract

The invention is to prevent dielectric breakdown of a capacitor in a semiconductor device having the capacitor and a MOS transistor formed on a same semiconductor substrate. A SiOfilm that is to be a gate insulation film of a high voltage MOS transistor is formed on a whole surface of a P-type semiconductor substrate. A photoresist layer is selectively formed in a high voltage MOS transistor formation region and on a part of a SiOfilm covering edges of trench isolation films adjacent to a capacitor formation region, and the SiOfilm is removed by etching using this photoresist layer as a mask. Since the photoresist layer functions as a mask in this etching, the edges of the trench isolation films adjacent to the capacitor are not cut too deep. The SiOfilm remaining in this etching and a SiOfilm to be formed thereafter form a capacitor insulation film.


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