The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 26, 2008
Filed:
Nov. 15, 2005
Sung-jin Kim, Hwaseong-si, KR;
Soon-moon Jung, Seongnam-si, KR;
Won-seok Cho, Suwon-si, KR;
Jae-hoon Jang, Hwaseong-si, KR;
Jong-hyuk Kim, Incheon, KR;
Kun-ho Kwak, Yongin-si, KR;
Hoon Lim, Seoul, KR;
Sung-Jin Kim, Hwaseong-si, KR;
Soon-Moon Jung, Seongnam-si, KR;
Won-Seok Cho, Suwon-si, KR;
Jae-Hoon Jang, Hwaseong-si, KR;
Jong-Hyuk Kim, Incheon, KR;
Kun-Ho Kwak, Yongin-si, KR;
Hoon Lim, Seoul, KR;
Abstract
Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same are provided. The semiconductor integrated circuit devices include an interlayer insulating layer formed on a semiconductor substrate and a single crystalline semiconductor plug penetrating the interlayer insulating layer. A single crystalline semiconductor body pattern is provided on the interlayer insulating layer. The single crystalline semiconductor body pattern has an elevated region and contacts the single crystalline semiconductor plug. The method of forming the single crystalline semiconductor body pattern having the elevated region includes forming a sacrificial layer pattern covering the single crystalline semiconductor plug on the interlayer insulating layer. A capping layer is formed to cover the sacrificial layer pattern and the interlayer insulating layer, and the capping layer is patterned to form an opening which exposes a portion of the sacrificial layer pattern. Subsequently, the sacrificial layer pattern is selectively removed to form a cavity in the capping layer, and a planarized single crystalline semiconductor body pattern is formed to fill the cavity and the opening.