The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2008
Filed:
Mar. 28, 2006
Kyu-dong Jung, Suwon-si, KR;
Woon-bae Kim, Suwon-si, KR;
In-sang Song, Seoul, KR;
Moon-chul Lee, Yongin-si, KR;
Jun-sik Hwang, Yongin-si, KR;
Suk-jin Ham, Seoul, KR;
Kyu-dong Jung, Suwon-si, KR;
Woon-bae Kim, Suwon-si, KR;
In-sang Song, Seoul, KR;
Moon-chul Lee, Yongin-si, KR;
Jun-sik Hwang, Yongin-si, KR;
Suk-jin Ham, Seoul, KR;
Samsung Electronics Co., Ltd., Suwon, KR;
Abstract
A packaging chip in which a circuit module is packaged and a method of packaging a circuit module are provided. The packaging chip includes a base wafer; a circuit module on the base wafer; a packaging wafer having a cavity and combined with the base wafer so that the circuit module fits inside the cavity; a connecting electrode connecting upper and lower surfaces of the cavity; and a seed layer between the connecting electrode and the packaging wafer. The method includes etching a lower surface of the packaging wafer to form a cavity, stacking a metal layer in an area of the lower surface, combining the base wafer with the packaging wafer, polishing the packaging wafer, forming a viahole through the packaging wafer, stacking a seed layer on the packaging wafer, plating the inside of the viahole, removing the seed layer and forming an electrode.