The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Aug. 05, 2008
Filed:
Jun. 23, 2005
Hisao Ichijo, Soraku-gun, JP;
Hiroyoshi Ogura, Kyoto, JP;
Yoshinobu Sato, Takatsuki, JP;
Teruhisa Ikuta, Ikoma, JP;
Hisao Ichijo, Soraku-gun, JP;
Hiroyoshi Ogura, Kyoto, JP;
Yoshinobu Sato, Takatsuki, JP;
Teruhisa Ikuta, Ikoma, JP;
Matsushita Electric Industrial Co., Ltd., Osaka, JP;
Abstract
An object of the present invention is to provide a semiconductor device that is able to realize a low on-resistance maintaining a high drain-to-source breakdown voltage, and a method for manufacturing thereof, the present invention including: a supporting substrate; a semiconductor layer having a Ptype active region that is formed on the supporting substrate, interposing a buried oxide film between the semiconductor layer and the supporting substrate; and a gate electrode that is formed on the semiconductor layer, interposing a gate oxide film and a part of a LOCOS film between the gate electrode and the semiconductor layer, wherein the Ptype active region has: an Ntype source region; a P type body region; a Ptype back gate contact region; an N type drain offset region; an Ntype drain contact region; and an N type drain buffer region that is formed in a limited region between the N type drain offset region and the P type body region, and the N type drain buffer region is in contact with a source side end of the LOCOS film and is shallower than the N type drain offset region.