The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 29, 2008
Filed:
Aug. 11, 2004
Richard J. Carter, Fairview, OR (US);
Wai Lo, Lake Oswego, OR (US);
Sey-shing Sun, Portland, OR (US);
Hong Lin, Vancouver, WA (US);
Verne Hornback, Camas, WA (US);
Richard J. Carter, Fairview, OR (US);
Wai Lo, Lake Oswego, OR (US);
Sey-Shing Sun, Portland, OR (US);
Hong Lin, Vancouver, WA (US);
Verne Hornback, Camas, WA (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A method to maintain a well-defined gate stack profile, deposit or grow a uniform gate dielectric, and maintain gate length CD control by means of an inert insulating liner deposited after dummy gate etch and before the spacer process. The liner material is selective to wet chemicals used to remove the dummy gate oxide thereby preventing undercut in the spacer region. The method is aimed at making the metal gate electrode technology a feasible technology with maximum compatibility with the existing fabrication environment for multiple generations of CMOS transistors, including those belonging to the 65 nm, 45 nm and 25 nm technology nodes, that are being used in analog, digital or mixed signal integrated circuit for various applications such as communication, entertainment, education and security products.