The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 08, 2008
Filed:
Nov. 03, 2004
Bart Van Schravendijk, Sunnyvale, CA (US);
Thomas W Mountsier, San Jose, CA (US);
Mahesh K Sanganeria, Sunnyvale, CA (US);
Glenn B Alers, Scots Valley, CA (US);
Roey Shaviv, Palo Alto, CA (US);
Bart van Schravendijk, Sunnyvale, CA (US);
Thomas W Mountsier, San Jose, CA (US);
Mahesh K Sanganeria, Sunnyvale, CA (US);
Glenn B Alers, Scots Valley, CA (US);
Roey Shaviv, Palo Alto, CA (US);
Novellus Systems, Inc., San Jose, CA (US);
Abstract
Methods of protecting exposed metal damascene interconnect surfaces in a process for making electronic components and the electronic components made according to such methods. An integrated circuit structure having damascene regions with exposed metal surfaces is provided into a closed processing chamber, whereby a first reactant is contacted to the exposed metal surfaces to transform a top portion of the metal layer into a protective self-aligned buffer layer. Reacting molecules of the first reactant with metal atoms of this metal layer forms the protective self-aligned buffer layer entirely within such metal layer. Alternatively, adsorbing surface-active reactant molecules onto the exposed metal surface forms the protective self-aligned buffer layer. A second reactant may be contacted to the protective self-aligned buffer layer to form a self-aligned dielectric cap layer directly over the protective self-aligned buffer layer.