The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jul. 08, 2008

Filed:

Jun. 18, 2007
Applicants:

Huajie Chen, Danbury, CT (US);

Dureseti Chidambarrao, Weston, CT (US);

Oleg G. Gluschenkov, Poughkeepsie, NY (US);

An L. Steegen, Stamford, CT (US);

Haining S. Yang, Wappingers Falls, NY (US);

Inventors:

Huajie Chen, Danbury, CT (US);

Dureseti Chidambarrao, Weston, CT (US);

Oleg G. Gluschenkov, Poughkeepsie, NY (US);

An L. Steegen, Stamford, CT (US);

Haining S. Yang, Wappingers Falls, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
H01L 21/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A process is provided for making a PFET and an NFET. Areas in a first semiconductor region adjacent to a gate stack are recessed. A lattice-mismatched semiconductor layer is grown in the recesses to apply a strain to the channel region of the PFET adjacent thereto. A layer of the first semiconductor material can be grown over the lattice-mismatched semiconductor layer and a salicide formed from the layer of silicon to provide low-resistance source and drain regions.


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