The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Sep. 12, 2006
Claude L. Bertin, South Burlington, VT (US);
Wayne F. Ellis, Jericho, VT (US);
Mark W. Kellogg, Essex Junction, VT (US);
William R. Tonti, Essex Junction, VT (US);
Jerzy M. Zalesinski, Essex Junction, VT (US);
James M. Leas, South Burlington, VT (US);
Wayne J. Howell, Williston, VT (US);
Claude L. Bertin, South Burlington, VT (US);
Wayne F. Ellis, Jericho, VT (US);
Mark W. Kellogg, Essex Junction, VT (US);
William R. Tonti, Essex Junction, VT (US);
Jerzy M. Zalesinski, Essex Junction, VT (US);
James M. Leas, South Burlington, VT (US);
Wayne J. Howell, Williston, VT (US);
International Business Machines Corporation, Armonk, NY (US);
Abstract
A plurality of semiconductor devices are provided on a carrier for testing or burning-in. The carrier is then cut up to provide single chip-on-carrier components or multi-chip-on-carrier components. The carrier is used as a first level package for each chip. Thus, the carrier serves a dual purpose for test and burn-in and for packaging. A lead reduction mechanism, such as a built-in self-test engine, can be provided on each chip or on the carrier and is connected to contacts of the carrier for the testing and burn-in steps. The final package after cutting includes at least one known good die and may include an array of chips on the carrier, such as a SIMM or a DIMM. The final package can also be a stack of chips each mounted on a separate carrier. The carriers of the stack are connected to each other through a substrate mounted along a side face of the stack that is electrically connected to a line of pads along an edge of each carrier.