The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jul. 01, 2008
Filed:
Dec. 12, 2006
Fumitaka Arai, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Yokohama, JP;
Nobutoshi Aoki, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Hiroshi Watanabe, Yokohama, JP;
Takamitsu Ishihara, Yokohama, JP;
Fumitaka Arai, Yokohama, JP;
Toshiyuki Enda, Zushi, JP;
Hiroyoshi Tanimoto, Yokohama, JP;
Naoki Kusunoki, Yokohama, JP;
Nobutoshi Aoki, Yokohama, JP;
Riichiro Shirota, Fujisawa, JP;
Hiroshi Watanabe, Yokohama, JP;
Takamitsu Ishihara, Yokohama, JP;
Kabushiki Kaisha Toshiba, Tokyo, JP;
Abstract
A NAND cell unit is formed with an advanced gate forming process on a semiconductor layer of a first conductivity type, which is formed on a semiconductor substrate of the first conductivity type with an insulating film interposed therebetween. First impurity-doped layers of a second conductivity type are formed on the semiconductor layer, which serve as channel regions of the select gate transistors Bit line contact- and source line contact-use second impurity-doped layers of the first conductivity type are formed at bit line and source line contact portions, sidewalls of which are covered with an insulating film.